A clear, beginner-friendly guide to mixed-criticality systems in physical AI and robotics: what they are, why they matter, the real engineering challenges, and how the industry is solving them today.
Robots are no longer just bolting car parts in a factory cage. They are walking hospital corridors, delivering parcels on city streets, and driving trucks on public highways. When a robot shares a space with a human, a mistake is not a bug report but a physical consequence.
That raises an uncomfortable engineering question: how do you run life-critical safety software and resource-hungry AI inference on the same piece of hardware, at the same time, without one interfering with the other? This is not a hypothetical. It is the core squeeze that every physical AI team faces right now.
The answer the industry keeps reaching for is called a mixed-criticality system. It sounds academic, but the concept is practical, urgent, and a little harder than most articles let on. This post breaks it down clearly so you can actually understand what is at stake.
A mixed-criticality system (MCS) is any computing platform that runs tasks of different safety importance side by side on the same hardware.
Think of a robot arm used in a surgical assist device. It might need to run:
All three need the CPU. But they are not equally important. If the logging service hangs, nothing bad happens. If the motor control loop misses its deadline because the vision model consumed too much memory bandwidth, someone could get hurt.
That tension — between performance and safety, on shared silicon — is exactly what mixed-criticality design tries to solve.
Traditional robotics was predictable. A factory arm repeated the same motion cycle thousands of times. You could test every scenario, certify the software, and ship.
Physical AI breaks that model. Neural networks are non-deterministic by nature. Their execution time varies depending on the input. A camera feed of an empty corridor takes different processing time than one filled with moving people. This variability is poison for real-time safety systems, which need guaranteed worst-case timing.
On top of that, AI models are hungry. A modern perception model can require tens of gigabytes of memory bandwidth per second. That bandwidth comes from the same shared memory bus that the safety-critical motor controller reads sensor data from.
The result: you have a fast-growing, hungry, unpredictable tenant (the AI workload) sharing an apartment with a tenant who absolutely cannot be disturbed (the safety controller). Making them coexist without conflict is the mixed-criticality squeeze.
When multiple tasks share a CPU or memory system, one task can slow down another simply by competing for the same resource. This is called timing interference.
For safety-critical tasks, you need to prove a worst-case execution time (WCET). That proof falls apart the moment a non-critical AI workload can arbitrarily delay memory access.
Modern multi-core chips make this worse. Cores share L2/L3 caches and DRAM controllers. A neural network running on core 1 can thrash the cache and stall the real-time controller running on core 2.
Safety standards like ISO 26262 (automotive) and IEC 61508 (industrial) require "freedom from interference." This means a low-criticality task must be proven unable to corrupt or delay a high-criticality one.
On a shared SoC, memory partitioning is the key technique. You assign dedicated memory regions (or even dedicated memory controllers) to safety-critical tasks so they are physically unreachable by other processes.
SoC Memory Layout (simplified example)
├── Safety-Critical Region (SRAM A)
│ ├── RTOS kernel
│ ├── Motor control task
│ └── Sensor fusion task
├── AI Inference Region (SRAM B + DRAM partition)
│ ├── Vision model weights
│ └── Inference runtime
└── General Purpose Region
├── Linux OS
├── Logging services
└── Cloud communication stackA standard scheduler prioritizes tasks by urgency. A mixed-criticality scheduler must also consider what happens when the system is under stress. When resources get tight, low-criticality tasks should degrade gracefully, but critical tasks must always meet their deadlines.
The challenge is that conventional priority-based schedulers do not make this distinction cleanly. Getting this wrong means the entertainment system can, in theory, delay the brakes.
Safety certification (ISO 26262, DO-178C, IEC 61508) is slow and expensive. Every change to the codebase can require re-certification. AI models, by contrast, are retrained frequently.
This creates a direct conflict: the part of the system that changes most often (the AI) is running next to the part that must be proven unchanging (the safety kernel). Teams need deployment architectures that let the AI layer update independently without triggering a full re-certification cycle.
A hypervisor sits below the operating systems and enforces hard boundaries between partitions. A safety RTOS runs in one partition; Linux with the AI stack runs in another. The hypervisor controls CPU time allocation, memory access, and interrupt routing between them.
Hardware (SoC)
└── Hypervisor (Type-1, certified)
├── Partition A: Safety RTOS
│ ├── Motor control
│ ├── Emergency stop
│ └── Sensor arbitration
└── Partition B: Linux (General)
├── AI inference engine
├── ROS2 nodes
└── OTA update daemonThe hypervisor enforces that Partition B cannot affect Partition A, even in a crash scenario. Commercial examples include Green Hills INTEGRITY, Wind River VxWorks, and Blackberry QNX.
Chip makers are building SoCs that dedicate separate silicon blocks to different criticality levels. The safety-critical core gets a lockstep processor (two cores running identical code to catch errors) and its own memory controller. The AI workload gets a GPU or NPU cluster.
Hardware-level separation means software isolation does not need to carry the full burden.
| Feature | Safety Domain | AI/General Domain |
|---|---|---|
| Processor type | Lockstep CPU | GPU / NPU cluster |
| Memory | Dedicated SRAM | Shared DRAM |
| Timing guarantee | Hard real-time | Best-effort |
| OS | Certified RTOS | Linux / Android |
| Update frequency | Rare, certified | Frequent, OTA |
Companies like Qualcomm and NEURA Robotics are working on standardized deployment interfaces that let AI workloads be validated and swapped without touching the safety stack. The goal is to let the AI layer evolve fast while the safety layer stays stable and certified.
Tools like memory coloring and hardware memory partitioning assign guaranteed bandwidth slices to critical tasks. Even if the AI model is running flat out, the safety controller always gets its reserved slice of DRAM bandwidth.
If it helps, think of a restaurant kitchen:
The rule: the dishwasher can never pile dishes on the head chef's counter. That is spatial isolation. The prep cook finishes their work during off-peak hours or in designated time slots. That is temporal isolation.
Mixed-criticality engineering is the architecture that enforces these rules in silicon and software.
Autonomous vehicles: A car running on NVIDIA Drive Thor or Qualcomm Snapdragon Ride runs ADAS safety tasks (emergency braking, lane keeping) on an isolated RTOS partition while vision models for perception and infotainment run on the Linux side.
Industrial robots: A collaborative robot (cobot) uses a certified safety controller for force/torque monitoring (which stops the arm if it touches a human) while a separate Linux partition runs AI-based task planning and vision.
Surgical robots: Real-time servo control runs on a certified processor with deterministic timing while an AI assistant for image analysis runs on a GPU partition with no safety certification required.
Here is the honest part. Mixed-criticality is not a solved problem.
Teams working on physical AI products today are navigating all of this in real time while also shipping products.
1. What is a mixed-criticality system in simple terms?
It is a computing platform that runs both safety-critical tasks and non-critical tasks on the same hardware, with strict rules to keep them from interfering with each other.
2. Why can you not just use two separate chips?
You can, and sometimes teams do. But two chips mean more cost, more power consumption, more weight, and a larger board. As robots get smaller and more power-constrained, running everything on one SoC becomes necessary.
3. What does "freedom from interference" mean?
It is a requirement in safety standards saying that a low-criticality process must be provably unable to delay, corrupt, or crash a high-criticality process. It covers both software (memory writes) and timing (cache pressure, bus contention).
4. What is a hypervisor in this context?
A Type-1 hypervisor is software that runs directly on the hardware (below any OS) and enforces strict partitions between different operating environments. It controls which partition gets CPU time, memory, and hardware access.
5. Can Linux run safely in a mixed-criticality system?
Linux is not safety-certified and is not real-time by nature. But it can run safely in a lower-criticality partition, isolated from the certified RTOS partition by a hypervisor. This is a very common pattern in automotive and robotics.
6. How do AI models cause timing problems for safety tasks?
Neural networks consume large amounts of memory bandwidth and cache. When they run on the same chip as a real-time safety task, they can slow down memory access for the safety task in unpredictable ways. This makes it impossible to guarantee worst-case execution time.
7. What safety standards apply to physical AI robots?
Common ones include ISO 10218 and ISO/TS 15066 for collaborative robots, ISO 26262 for automotive systems, IEC 61508 for industrial equipment, and IEC 62061 for machinery safety. Which standard applies depends on the application domain.
8. What is the role of an RTOS in a mixed-criticality robot?
A real-time operating system (RTOS) provides deterministic task scheduling, meaning it can guarantee that a task will always run within a defined time window. This predictability is essential for motor control, sensor fusion, and emergency response.
9. Can AI components ever be safety-certified?
Increasingly, yes. ISO/PAS 8800 (AI in road vehicles) and EASA guidance for aviation AI are emerging frameworks. But certifying a neural network is still far more complex than certifying traditional control software, and the tools are still maturing.
10. What is the "physical AI squeeze" the title refers to?
It is the conflict between two opposing pressures on a single chip: the demand for more AI compute power (which is powerful but unpredictable and resource-hungry) and the demand for certified safety behavior (which requires predictability, isolation, and formal guarantees). Solving both on one SoC is the squeeze.
What Are Mixed-Criticality OS Environments? - https://www.windriver.com/solutions/learning/what-are-mixed-criticality-os-environments
Garofalo, A. et al. A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications - https://arxiv.org/abs/2502.18953
What is Mixed Criticality? - https://www.trentonsystems.com/en-us/resource-hub/blog/what-is-mixed-criticality
Cunha, L. et al. System-Level Isolation for Mixed-Criticality RISC-V SoCs: A ”World” Reality Check - https://arxiv.org/html/2602.05002
NEURA Robotics and Qualcomm Enter Strategic Collaboration to Advance Physical AI and Cognitive Robotics - https://neura-robotics.com/neura-qualcomm-collaboration-physical-ai/
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